1. Field of the Invention
The present invention relates to a complementary circuit device, and more particularly, it relates to a CMOS (complementary metal-oxide-semiconductor) integrated circuit which is automatically released from a latch-up phenomenon for returning to an operating state.
2. Description of the Background Art
In general, a latch-up phenomenon may occur in a CMOS integrated circuit due to its structure. The latch-up phenomenon is such a phenomenon that a bipolar transistor (thyristor) formed in relation to the CMOS structure is triggered by some external factor to enter a conducting state during normal logical circuit operation of the CMOS integrated circuit, whereby an excessive source current flows to the CMOS structure. If such a latch-up phenomenon occurs during operation of an integrated circuit (IC), normal logical circuit operation cannot be performed. Besides, the IC may be broken if the latch-up state is prolonged.
In order to restore the IC to a normal operating state upon occurrence of such a latch-up phenomenon, it is necessary to interrupt power supply to the IC.
The principle operation of the latch-up phenomenon is disclosed in a number of documents. With reference to FIGS. 1 and 2, the said principle of operation is now briefly described.
A CMOS semiconductor device shown in FIG. 1 defines a CMOS inverter, an equivalent circuit of which is shown in FIG. 2. Referring to FIG. 1, an N.sup.- well 4 is formed in a P.sup.- semiconductor substrate 2, and a P-channel MOS transistor 6 is formed in the N.sup.- well 4. The P-channel MOS transistor 6 includes P.sup.+ source and drain regions 8 and 10 formed on the N.sup.- well 4, a gate insulating film 12 formed in a region between the P.sup.+ source and drain regions 8 and 10 on a surface part of the N.sup.- well 4, and a gate electrode 14 formed on the gate insulating film 12.
An N-channel MOS transistor 16 is formed on a part of the P.sup.- semiconductor substrate 2 other than that provided with the N.sup.- well 4. The N-channel MOS transistor 16 includes N.sup.+ source and drain regions 18 and 20 formed on the P.sup.- semiconductor substrate 2, a gate insulating film 22 formed in a region between the N.sup.+ source and drain regions 18 and 20 on a surface part of the P.sup.- semiconductor substrate 2, and a gate electrode 24 formed on the gate insulating film 22. The gate electrodes 14 and 24 are connected to an input terminal. The P.sup.+ source region 8 and the N.sup.+ drain region 20 are connected to an output terminal 26. A power terminal 28 applies source voltage V.sub.CC to the P.sup.+ drain region 10, and a ground terminal 30 applies ground voltage V.sub.SS to the N.sup.+ source region 18.
In this example, an N.sup.+ P.sup.- N.sup.- transistor Tr1 is transversely defined as a parasitic transistor by the N.sup.+ source region 18 serving as an emitter, the P.sup.- semiconductor substrate 2 serving as a base and the N.sup.- well 4 serving as a collector. Further, a P.sup.+ N.sup.- P.sup.- transistor Tr2 is vertically defined by the P.sup.+ drain region 10 serving as an emitter, the N.sup.- well 4 serving as a base and the P.sup.- semiconductor substrate 2 serving as a collector.
Referring to FIG. 3, parasitic resistance Ra1 is formed between the N.sup.- well 4 and the power terminal 28. Parasitic resistance Ra0 is formed between the P.sup.+ drain region 10 and the power terminal 28. Parasitic resistance Rb0 is formed between the N.sup.+ source region 18 and the ground terminal 30. Parasitic resistance Rb1 is formed between the P.sup.- semiconductor substrate 2 and the ground terminal 30.
It is assumed that the CMOS semiconductor device shown in FIG. 1 is in an operating state. Description is now made on operation performed when the power terminal 28 receives positive noise. Referring to FIGS. 1 to 3, it is assumed that relations Ra0&lt;Ra1 and Rb0&lt;Rb1 hold. In this case, there is such possibility that the potential of the P.sup.+ drain region 10 serving as the emitter of the transistor Tr2 is higher than that of the N.sup.- well 4 serving as the base of the transistor Tr2, due to the aforementioned noise. If conditions are satisfied, injection is caused from the emitter of the transistor Tr2, i.e., the P.sup.+ drain region 10, into the base, i.e., the N.sup.- well 4. The transistor Tr2 enters an on state. In this case, the current flowing from the emitter, i.e., the P.sup.+ drain region 10 into the transistor Tr2 is amplified by the transistor Tr2 due to the characteristics of the bipolar transistor, to flow into the collector, i.e., the P.sup.- semiconductor substrate 2. This current is referred to as Ia.
Between the base of the transistor Tr1, i.e., the P.sup.- semiconductor substrate 2, the ground terminal 30 and the emitter, i.e., the N.sup.+ source region 18, potential difference is developed by the parasitic resistance Rb1. Since the relation Rb0&lt;Rb1 holds, injection is caused from the base of the transistor Tr1, i.e., the P.sup.- semiconductor substrate 2 into the emitter, i.e., the N.sup.+ source region 18. Consequently, the transistor Tr1 is turned on. Then, a current Ib flows from the collector of the transistor Tr1, i.e., the N.sup.- well 4 to the emitter, i.e., the N.sup.+ source region 18. The transistors Tr1 and Tr2 remain in on states so far as the current flows.
In this case, the aforementioned circuit forms a thyristor as shown in FIG. 4. In this thyristor, currents flow from the power terminal 28 to the ground terminal 30 if an appropriate current is supplied to a gate 32 when the power terminal 28 is at a plus potential with respect to the ground terminal 30. It is known that these currents continuously flow unless the potential of the power terminal 28 is made identical to that of the ground terminal 30. In other words, the currents Ia and Ib shown in FIG. 3 continuously flow unless the power is interrupted.
This phenomenon is called a latch-up phenomenon. In a CMOS integrated circuit, such a latch-up phenomenon may occur due to its structure.
Various countermeasures have been generally proposed in order to prevent the latch-up phenomenon. FIG. 5 shows an example of such a countermeasure. The circuit shown in FIG. 3 will not define a thyristor unless conditions Ra0&lt;Ra1 and Rb0&lt;Rb1 hold for Ra0, Ra1, Rb0 and Rb1. In the example shown in FIG. 5, bases and emitters of parasitic transistors Tr1 and Tr2 are made to have the same potentials, so that the aforementioned conditions will not hold.
Referring to FIG. 5, an N.sup.- well 4 is formed in a P.sup.- semiconductor substrate 2, and a P-channel MOS transistor 6 is formed in the N.sup.- well 4. The P-channel MOS transistor 6 includes P.sup.+ source and drain regions 8 and 10 formed on the N.sup.- well 4, a gate insulating film 12 formed in a region between the P source and drain regions 8 and 10 on a surface part of the N.sup.- well 4, and a gate electrode 14 formed on the gate insulating film 12.
An N-channel MOS transistor 16 is formed on a part of the P.sup.- semiconductor substrate 2 other than that provided with the N.sup.- well 4. The N-channel MOS transistor 16 includes N.sup.+ source and drain regions 18 and 20 formed on the P.sup.- semiconductor substrate 2, a gate insulating film 22 formed in a region between the N.sup.+ source and drain regions 18 and 20 on a surface part of the P.sup.- semiconductor substrate 2, and a gate electrode 24 formed on the gate insulating film 22.
The gate electrodes 14 and 24 are connected to an input terminal. The P.sup.+ source region 18 and the N.sup.+ drain region 20 are connected to an output terminal 26. A power terminal 28 applies source voltage V.sub.CC to the P.sup.+ drain region 10. A ground terminal 30 applies ground voltage V.sub.SS to the N.sup.+ source region 18. The above structure is similar to that of the CMOS semiconductor device shown in FIG. 1.
The CMOS semiconductor device shown in FIG. 5 further includes a P.sup.+ diffusion region 34 which is formed on a surface part of the P.sup.- semiconductor substrate 2 held between the N.sup.+ drain region 20 and the N.sup.- well 4 in a spaced-apart manner, and an N.sup.+ diffusion region 36 formed on a surface part of the semiconductor substrate 2 held between the P.sup.+ diffusion region 34 and the N.sup.- well 4, to be spaced apart from the P.sup.+ diffusion region 34 and adjacent to the N.sup.- well 4. The P.sup.+ diffusion region 34 is connected to the ground terminal 30. The N.sup.+ diffusion region 36 is connected to the power terminal 28.
The P.sup.+ diffusion region 34 connects the ground terminal 30 to the P.sup.- semiconductor substrate 2. The N.sup.+ diffusion region 36 connects the power terminal 28 to the N.sup.- well 4. Consequently, the parasitic resistance Rb1 as well as the parasitic resistance Ra1, which are shown in FIG. 3, are extremely reduced. Thus, the aforementioned conditions for the latch-up phenomenon are hardly satisfied. Namely, it is substantially impossible to simultaneously satisfy both conditions Ra0&lt;Ra1 and Rb0&lt;Rb1.
However, the circuit pattern of the latch-up preventing circuit shown in FIG. 5 is so complicated that the transverse area of the integrated circuit is increased. Particularly since refinement of an integrated circuit is strongly required nowadays, it is not preferable to hinder such refinement in order to prevent the latch-up phenomenon.
To this end, demanded is a technique which can prompt refinement of a CMOS integrated circuit, while protecting the same against bad influence exerted by the latch-up phenomenon. FIG. 6 shows an exemplary technique developed for such an object. This complementary circuit device is disclosed in Japanese Patent Laying-Open No. 59-202659. The invention relating to the complementary circuit device shown in FIG. 6 is not directly aimed at preventing a latch-up phenomenon caused in a CMOS integrated circuit, but the object thereof is to automatically cancel a latch-up phenomenon occurring in a CMOS integrated circuit and restore the same to an operating state.
Referring to FIG. 6, the conventional complementary circuit device includes a CMOS integrated circuit 42 which is connected between a first power source 38 and a second power source 40, latch-up detection means 44 which is connected between the first power source 38 and the CMOS integrated circuit 42 for detecting a latch-up phenomenon occurring in the CMOS integrated circuit 42, and switching means 46 which is connected between the second power source 40 and the CMOS integrated circuit 42 for cutting an energization path to the CMOS integrated circuit 42 on the basis of an output from the latch-up detection means 44. The latch-up detection means 44 is formed by means for detecting a current flowing in the CMOS integrated circuit 42, for example.
With reference to FIG. 6, the operation of this complementary circuit device is now described. When the CMOS integrated circuit 42 normally operates, the switching means 46 is closed. A weak current flows from the second power source 40 to the first power source 38. In response to this weak current, the latch-up detection means 44 sends a signal indicating the normal operating state to the switching means 46. The switching means 46 is in a conducting state while the same receives the signal indicating the normal operating state. In other words, a prescribed current is supplied to the CMOS integrated circuit 42 when the same is in the normal operating state.
When a latch-up phenomenon occurs in the CMOS integrated circuit 42 due to some cause, the current passing through the CMOS integrated circuit 42 is increased. The latch-up detection means 44 detects the increase in the current passing through the CMOS integrated circuit 42, for example, and sends a signal indicating the current abnormality to the switching means 46. The switching means 46 cuts the energization path in response to the signal indicating the current abnormality. Thus, the CMOS integrated circuit 42 is released from the latch-up phenomenon since the current is interrupted.
When the latch-up phenomenon is thus cancelled, the current flowing in the energization path is by far reduced as compared with that in the latch-up phenomenon. In response to such reduction of the current, the latch-up detection means 44 stops transmission of the signal indicating the current abnormality. Consequently, the switching means 46 re-enters the conducting state. A current is supplied to the CMOS integrated circuit 42, which in turn re-starts its operation. Thus, the complementary circuit device shown in FIG. 6 can detect occurrence of a latch-up phenomenon and automatically cancel the same, to return to its operating state. According to this method, it is possible to effectively cope with a latch-up phenomenon without hindering refinement of the CMOS integrated circuit.
However, the conventional complementary circuit device has the following problems: One of the problems is that the types of CMOS integrated circuits applicable to the circuit shown in FIG. 6 are restricted. For example, types of logical circuits which are assembled into integrated circuits are classified into that whose output is determined by only combination of inputs at a certain point of time and that whose output is determined by combination of not only inputs at a certain point of time but states in advance thereof. The former is called a combinational logical circuit, and the latter is called a sequential logical circuit.
Suppose that the aforementioned CMOS integrated circuit includes only a combinational logical circuit. In this case, the output of the CMOS integrated circuit is automatically set by combination of external inputs at a certain point of time, so far as the CMOS integrated circuit is in an operable state. Therefore, the CMOS integrated circuit correctly operates so far as the external inputs are correct.
On the other hand, suppose that the aforementioned CMOS integrated circuit includes a sequential logical circuit. In general, a sequential logical circuit includes a memory circuit which holds information in some form. When a latch-up phenomenon occurs in this CMOS integrated circuit, a large current flows within the circuit in a portion which is not the original energization path. Thus, the CMOS integrated circuit enters an absolutely disordered state. When the switching means 46 interrupts the current to the CMOS integrated circuit and re-starts supply of the current, the content of the memory circuit included in the CMOS integrated circuit is undefined. Namely, there is a strong possibility that the information forming the basis for the operation of the sequential logical circuit is destroyed.
Therefore, the conventional latch-up cancelling technique must not be applied at least to a CMOS integrated circuit including a sequential logical circuit. The types of logical circuits included in a CMOS integrated circuit are increased as the circuit scale is increased. It may be considered that the possibility for application of the conventional latch-up cancelling technique is reduced.
Another problem is that a complementary circuit device integrated with the latch-up cancelling technique has low reliability in operation upon occurrence of a latch-up phenomenon. Consider that the conventional latch-up cancelling technique is applied to the aforementioned CMOS integrated circuit including the sequential logical circuit. In this case, at least it is possible to automatically cancel a latch-up phenomenon and restore the circuit to the operating state. The problem is that accuracy of operation after the restoration is not guaranteed. The cancellation of the latch-up phenomenon and the restoration to the operating state are automatically performed. Therefore, a user of an apparatus assembled with such a CMOS integrated circuit cannot immediately detect abnormality of the operation.
Description is now made on such case that the conventional latch-up cancelling technique is applied to circuit structure which determines operation procedure by a program counter, such as a microcomputer employing a CMOS integrated circuit, for example. Referring to FIG. 7, symbols A to K denote prescribed addresses in a program storage region. Hatched portions A-B, C-D and E-F are regions storing a group of instructions employed for executing certain operation. An instruction is fetched from a prescribed address of the program storage region in accordance with the content of a program counter, to execute the operation. For example, the program is generally executed in order of A-B, C-D and E-F, as shown in FIG. 7(a).
It is assumed that a latch-up phenomenon occurs in the microcomputer during execution of an instruction from the address I. When the microcomputer is released from the latch-up phenomenon by the conventional latch-up cancelling technique and returns to the operating state, the content of the program counter is undefined.
For example, suppose that the microcomputer returns to the operating state when the program counter indicates the address J. The microcomputer must operate along the order of C-D and E-F. In this case, however, the microcomputer operates in order of C-I and J-F, as shown in FIG. 7(b). The command between I-D and E-J is not executed. When there is an apparatus which is controlled by this microcomputer, the apparatus may cause a significant malfunction. What is worse, operation following the address J is apparently normally continued if the operation is performed along the procedure shown in FIG. 7(b). Thus, the operator may miss the abnormality. Further, a small malfunction may result in a significant failure although the same will cause no bad problem if the same is appropriately coped with upon restoration of the microcomputer to the operating state.
Description is now made on a second example, in which the microcomputer returns to the operating state when the program counter indicates the address K. As shown in FIG. 7(c), the microcomputer re-starts operation from an address which is not the original program region. Thus, operation absolutely foreign to the operation of the microcomputer itself may be performed. Further, the operation of the microcomputer may form an infinite loop. A significant result may be caused also in this case.
Still another problem is that, in the conventional complementary circuit device, the latch-up phenomenon is easily repeated with only a relatively short time interval after cancellation thereof. Once a latch-up phenomenon occurs, therefore, the conventional complementary circuit device cannot perform stable operation.